This was necessary due to the complex ways to read bus frequency on all AMD Zen generations. In some cases the readout has to fall back to reading the CPU's LAPIC timer, which is error-prone especially on high load scenarios. So starting with HWiNFO 7.30 (and BenchMate 10.12) a bus frequency derived from the LAPIC tiemr is only read once during initialization to avoid irregular values. That means any bclock changes between BenchMate's initialization and the end of a benchmark run will not be reflected in the bus-dependent frequencies shown on the result dialog.
We mitigated the problem with two new features. At HWiNFO init we read the bus detection method to know if the bus clock will be unreliable. In addition we check the LAPIC timer between init and the end of a run and if a skew of more than 0.2% is detected, all bus-dependent clocks will be marked as "unreliable" and a warning appears on the bottom of the result dialog. 0.2% is the equivalent of 10 MHz on a 5000 MHz core frequency.
For us it is always important to show reliable information and communicate edge cases as good as possible. The new bus frequency reliability check lets you know, when AMD Zen frequencies are not to be taken for granted.
To get reliable frequencies derived from the bus, we ultimately need a solution from AMD.